A floating-gate technology for digital CMOS processes

We discuss the possibility of developing high-quality oating-gate memories and circuits in digital CMOS technologies that have only one layer of polysilicon. Here, the primary concern is whether or not we can get adequate control-gate linearity from MOS capacitors. We employ two experimental proceedures to address this issue and nd acceptable oating-gate circuit behavior with MOS capacitors. First, we simultaniously characterize a MOS capacitor and a linear capacitor; the experimental data show that MOS capacitors behave similarly to linear capacitors over a nite, but usable range. Second, we characterize two typical oating-gate MOS circuit primatives, a oating-gate ampli-er and a multiple-input translinear element, two basic circuits that rely heavily on the linearity of the capacitors that couple into the oating gates. Our measurements show that oating-gate circuits with MOS-capacitor control gates behave like their counterparts built with linear capacitors over speciic regions of operation. 1. INTRODUCTION Recently, there has been a tremendous amount of interest in using multiple-input oating-gate MOS (FGMOS) transistors to build circuits that process information by linearly summing a number of input voltages on the oating-gate via a capacitive voltage divider 3]. Nearly all such FG-MOS circuits have been developed in CMOS processes with two levels of polysilicon. Unfortunately, the second poly layer results in signiicantly higher fabrication costs; consequently , this option is now found in only a small percentage of current commercial processes. Our motivation for this work is to demonstrate that we can build high-performance, oating-gate memories and circuits in digital CMOS processes that have only one layer of polysilicon. The primary issue is whether or not we can obtain adequate control-gate linearity with MOS capacitors. Current research in a similar vein for switched-capacitor circuits gives us reasonable hope of similar results for FGMOS circuits 1]. The focus of this paper is to address the performance of FGMOS circuits using MOS-capacitor control gates. Figure 1 shows the experimental setup that we use to measure the capacitance-voltage characteristics of our candidate control-gate capacitors; the circuit shown is completely integrated on a single chip. With this circuit arrangement , we can measure the capacitance-voltage relationship of a capacitor using dc voltage sweeps or with simple gain measurements. Thus, we have a direct method